计算机组成与设计-硬件/软件接口-(第5版)-(MIPS版)-(英文版.亚洲版)

Preface vAbout the Author xiiiCHAPTERS1 Computer Abstractions and Technology 21.1 Introduction 31.2 Eight Great Ideas in Computer Architecture 111.3 Below Your Program 131.4 Under the Covers 161.5 Technologies for Building Processors and Memory 241.6 Performance 281.7 The Power Wall 401.8 The Sea Change： The Switch from Uniprocessors to Multiprocessors 431.9 Real Stuff： Benchmarking the Intel Core i7 461.10 Fallacies and Pitfalls 491.11 Concluding Remarks 521.12 Historical Perspective and Further Reading 541.13 Exercises 542 Instructions： Language of the Computer 602.1 Introduction 622.2 Operations of the Computer Hardware 632.3 Operands of the Computer Hardware 662.4 Signed and Unsigned Numbers 732.5 Representing Instructions in the Computer 802.6 Logical Operations 872.7 Instructions for Making Decisions 902.8 Supporting Procedures in Computer Hardware 962.9 MIPS Addressing for 32-Bit Immediates and Addresses 1062.10 Parallelism and Instructions： Synchronization 1162.11 Translating and Starting a Program 1182.12 A C Sort Example to Put It All Together 1262.13 Advanced Material： Compiling C 1342.14 Real Stuff： ARMy7 （32-bit） Instructions 1342.15 Real Stuff： x86 Instructions 1382.16 Real Stuff： ARMv8 （64-bit） Instructions 1472.17 Fallacies and Pitfalls 1482.18 Concluding Remarks 1502.19 Historical Perspective and Further Reading 1522.20 Exercises 1533 Arithmetic for Computers 1643.1 Introduction 1663.2 Addition and Subtraction 1663.3 Multiplication 1713.4 Division 1773.5 Floating Point 1843.6 Parallelism and Computer Arithmetic： Subword Parallelism 2103.7 Real Stuff： Streaming SIMD Extensions and Advanced Vector Extensions in x86 2123.8 Going Faster： Subword Parallelism and Matrix Multiply 2133.9 Fallacies and Pitfalls 2173.10 Concluding Remarks 2203.11 Historical Perspective and Further Reading 2243.12 Exercises 2254 The Processor 2304.1 Introduction 2324.2 Logic Design Conventions 2364.3 Building a Datapath 2394.4 A Simple Implementation Scheme 2474.5 An Overview ofPipelining 2604.6 Pipelined Datapath and Control 2744.7 Data Hazards： Forwarding versus Stalling 2914.8 Control Hazards 3044.9 Exceptions 3134.10 Parallelism via Instructions 3204.11 Real Stuff： The ARM Cortex-A8 and Intel Core i7 Pipelines 3324.12 Going Faster： Instruction-Level Parallelism and Matrix Multiply 3394.13 Advanced Topic： An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 3424.14 Fallacies and Pitfalls 3434.15 CondudingRemarks 3444.16 Historical Perspective and Further Reading 3454.17 Exercises 3455 Large and Fast： Exploiting Memory Hierarchy 3605.1 Introduction 3625.2 Memory Technologies 3665.3 The Basics of Caches 3715.4 Measuring and Improving Cache Performance 3865.5 Dependable Memory Hierarchy 4065.6 Virtual Machines 4125.7 Virtual Memory 4155.8 A Common Framework for Memory Hierarchy 4425.9 Using a Finite-State Machine to Control a Simple Cache 4495.10 Parallelism and Memory Hierarchies： Cache Coherence 4545.11 Parallelism and Memory Hierarchy： Redundant Arrays of Inexpensive Disks 4585.12 Advanced Material： Implementing Cache Controllers 4585.13 Real Stuff： The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 4595.14 Going Faster： Cache Blocking and Matrix Multiply 4635.15 Fallacies and Pitfalls 4665.16 GoncludingRemarks 4705.17 Historical Perspective and Further Reading 4715.18 Exercises 4716 Parallel Processors from Client to Cloud 4886.1 Introduction 4906.2 The Difficulty of Creating Parallel Processing Programs 4926.3 SISD， MIMD， SIMD， SPMD， and Vector 4976.4 Hardware Multithreading 5046.5 Multicore and Other Shared Memory Multiprocessors 5076.6 Introduction to Graphics Processing Units 5126.7 Clusters， Warehouse Scale Computers， and Other Message-Passing Multiprocessors 5196.8 Introduction to Multiprocessor Network Topologies 5246.9 Communicating to the Outside World： Cluster Networking 5276.10 Multiprocessor Benchmarks and Performance Models 5286.11 Real Stuff： Benchmarking Intel Core i7 versus NVIDIA Tesla GPU 5386.12 Going Faster： Multiple Processors and Matrix Multiply 5436.13 Fallacies and Pitfalls 5466.14 Concluding Remarks 5486.15 Historical Perspective and Further Reading 5516.16 Exercises 551APPENDICESA Assemblers， Linkers， and the SPiM Simulator A-2A.1 Introduction A-3A.2 Assemblers A-IOA.3 Linkers A-18A.4 Loading A-19A.5 Memory Usage A-20A.6 Procedure Call Convention A-22A.7 Exceptions and Interrupts A-33A.8 Input and Output A-38A.9 SPIM A-40A.10 MIPS R2000 Assembly Language A-45A.11 Concluding Remarks A-81A.12 Exercises A-82B TH-2 High Performance Computing System B-2B.1 Introduction B-3B.2 Compute Node B-3B.3 The Frontend Processors B-5B.4 The Interconnect B-6B.5 The Software Stack B-7B.6 LINPACK Benchmark Run （HPL） B-7B.7 Concluding Remarks B-8F Networks-on-Chip F-2F.1 Introduction F-3F.2 Communication Centric Design F-3F.3 The Design Space Exploration ofNoCs F-5F.4 Router Micro-architecture F-8F.5 Performance Metric F-9F.6 Concluding Remarks F-9Index I-1