FPGA芯片架构设计与实现

第1 章 FPGA 架构总体设计 ········································································· 1
1.1 FPGA 芯片研制流程·········································································· 1
1.2 FPGA 架构设计流程·········································································· 7
1.3 FPGA 规模和资源划分 ····································································· 17
1.4 FPGA 中功能模块划分 ····································································· 20
本章参考文献 ······················································································ 26
第2 章 FPGA 中时钟网络 ·········································································· 30
2.1 简介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 时钟网络设计方法 ·········································································· 43
2.4 时钟网络的灵活性 ·········································································· 48
2.5 路由级联 ······················································································ 51
2.6 仿真实验 ······················································································ 55
2.7 时钟网络热学建模 ·········································································· 61
2.8 仿真实验 ······················································································ 62
本章参考文献 ······················································································ 66
第3 章 FPGA 中电源/地线网络和漏电流 ······················································· 68
3.1 电源/地线网络 ··············································································· 68
3.2 IR-DROP 分析与优化 ········································································ 71
3.3 漏电流组成 ··················································································· 73
3.4 降低漏电流的方法 ·········································································· 74
3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真实验 ······················································································ 81
3.7 不均匀测试点的IR-DROP 求解 ··························································· 87
3.8 FPGA 电源网络IR-DROP 分析 ···························································· 89
本章参考文献 ······················································································ 94
第4 章 FPGA 中可编程逻辑单元 ································································· 98
4.1 基于多路选择器的逻辑单元 ······························································ 98
4.2 基于四输入LUT 的可编程逻辑单元的设计 ·········································· 102
4.3 LUT 的模型与实现 ········································································ 103
4.4 LUT 的输入数目K 的确定 ······························································· 106
4.5 进位逻辑 ····················································································· 109
4.6 基于查找表结构的FPGA 的不足 ······················································· 115
4.7 AIC 结构逻辑簇 ············································································ 117
4.8 基于AIC 结构FPGA 的逻辑簇 ························································· 120
4.9 面向AIC 的映射工具及结构评估平台 ················································ 124
4.10 结构特征匹配的AIC 簇互连优化 ···················································· 125
4.11 仿真分析和比较 ·········································································· 131
本章参考文献 ····················································································· 133
第5 章 FPGA 中可编程I/O 模块 ································································· 136
5.1 可编程I/O 系统结构 ······································································ 136
5.2 IOE 中的可编程输入缓冲器设计 ······················································· 138
5.3 IOE 中的可编程输出缓冲器设计 ······················································· 144
5.4 可编程I/O 的后端版图设计······························································ 156
5.5 高可靠I/O 模块的后端版图与测试 ····················································· 166
5.6 可编程I/O 的供电策略 ··································································· 172
5.7 全芯片IO 的ESD 技术 ····················································